1. Field of the Invention
The present invention relates to a thin film semiconductor device used for an image display device or the like.
2. Description of the Related Art
For a thin film where conventional thin film semiconductor devices, which are thin film transistors (TFTs) chiefly used for the image display device or the like, are formed, high temperature poly-Si has been predominantly employed. The high temperature poly-Si is constituted by polycrystalline silicon (Si) formed on a quartz substrate by high temperature heat treatment at a temperature of about 900° C. The polycrystalline Si having a comparatively large grain diameter of 500-600 nm is thereby formed. The TFTs formed on the high temperature poly-Si use a Si thin film with a low grain boundary density and high crystallinity as channels. Thus, it can attain an electron mobility of 100 to 150 cm2/Vs, which is near the electron mobility of single-crystal Si (−500 cm2/VS, S. M. Sze, Physics of Semiconductor Devices, p. 29, Second Edition, Wiley). However, in order to endure a high temperature process, there is a need to employ an expensive quartz substrate for this high temperature poly-Si. For this reason, a cost reduction in the overall device is difficult due to a cost of the substrate. The widespread use of TFTs has been thereby limited.
In recent years, in place of the high temperature poly-Si, use of low temperature poly-Si has been increasingly studied. The low temperature poly-Si is polycrystalline Si obtained by crystallizing amorphous Si formed on a low-cost glass or plastic substrate by a plasma CVD method, using a melting and recrystallizing method such as excimer laser annealing. With this approach, a polycrystalline Si thin film can be formed at a low temperature up to 150° C. Thus, a very cheap TFT can be formed. The low temperature poly-Si hitherto formed, however, had a grain size smaller than the high temperature poly-Si, and its surface roughness became noticeable. Further, only the polycrystalline Si with random surface orientations could be formed. When crystal grains are small, the density of grain boundaries in a carrier path increases. On the other hand, when the surface roughness is large, a breakdown voltage with respect to a gate voltage decreases. Further, when the surface orientations are random, trap level density of a grain boundary relatively increases. In either case, transistor characteristics are deteriorated. For this reason, the electron effect mobility of TFTs manufactured, using the conventional low temperature poly-Si as a material for the devices, was limited to approximately 150 cm2/Vs. With such a small electron mobility, a required device speed cannot be achieved. Thus, a problem arises that the types of devices that can be formed on the identical glass or plastic substrate are limited. In the case of an image display device, for example, a pixel unit can be formed on glass or plastic, but other circuits such as for a source driver, a gate driver, a decoder, a buffer, a shift register, a digital-to-analog converter, and a peripheral controller must be formed on a conventional printed circuit board. Then, the peripheral circuit unit and the substrate must be connected by a cable terminal for use. With this method, the size of a screen is reduced. In addition, the cost of the overall device increases.
In order to solve these problems, a technique for increasing the diameter of a crystal grain, planarizing a surface of the film, and aligning positions of crystal grains and their surface orientations is required. There have been proposed various techniques for increasing the crystal grain diameter, planarizing the film surface, and controlling the crystal grain positions and their surface orientations of the low temperature poly-Si. One such technique is disclosed in JP-A-7-321339. In this technique, a metal element for selectively promoting crystallization is introduced into an amorphous Si film formed on an insulating substrate to bring about growth of crystals in parallel with the substrate, thereby forming polycrystalline Si having a [111] axis in a carrier moving direction. Another technique is disclosed in JP-A-10-41234. In this technique, the shape of a beam for heat treatment and the moving amount of irradiation are precisely controlled, thereby forming rectangular polycrystalline Si having a <100> axis in a direction perpendicular to the substrate and a {220} surface in parallel with or at a 45 degrees with respect to a beam scanning direction. Another such technique is disclosed in JP-A-8-55808. In this technique, a first polycrystalline Si layer is formed on the substrate and seed crystals having one of specific surfaces {100}, {110}, and {111} are formed by anisotropic etching. Then, a second polycrystalline Si layer is formed thereon, thereby forming a layer of columnar polycrystalline Si having aligned surface orientations. However, in spite of these numerous attempts, a TFT with a sufficiently high mobility has thus far not been achieved.
The above-mentioned crystallization methods cannot be said to adequately fulfill the above desired requirements. For example, in these prior techniques, the maximum attainable grain diameter was about 2 μm, which is an inadequate value. This is less than about 8 μm, which is the practical size of a thin film transistor required for a large-screen liquid crystal display panel, much less for enabling reduction in device variations due to positional deviation of crystal grains. The more important problem is roughness of a Si thin film surface. In the crystallization method using a laser, especially an excimer laser, due to volume expansion during a melting and solidifying process of silicon, crystal grains collide with each other to lift up grain boundaries, thereby forming projections of the grain boundaries. In the case of annealing using the excimer laser, these projections are actually so high that they correspond to the film thickness of the original Si thin film. They sometimes extend to even 50 to 100 nm. If these projections are formed, the breakdown voltage with respect to the gate voltage is remarkably reduced, so that a gate leakage current is readily produced. For this reason, under present circumstances, though the mobility is expected to be traded off, the thickness of the gate insulation film is increased, as a measure against this reduction in the breakdown voltage. These techniques have not reached a level to replace an existing low-function thin film transistor device. Further, optimum lattice structures or optimum crystal surface orientations of Si crystals in contact with the substrate are not realizable from these techniques, which are also a cause of the above-mentioned problems, and which lead to an intrinsic limit as determined by deformation of an interface between the silicon crystals and the substrate, irrespective of methods for film formation and heat treatment.